Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Enabling the Next Generation of 5G Platforms (WP029)

Radio access networks (RANs) and associated core network hierarchy, which link end-user equipment to both the central telecom network and the cloud, are essential in building ubiquitous cellular connectivity to expand the number and breadth of use cases that can be supported by the technology. This paper outlines the current status of 5G standards and rollout, summarizes the new use cases 5G RANs need to support and examines the standards evolution to support higher bandwidth and additional use cases. Finally, it also explains how Achronix FPGA technology can be utilized by developers to meet the fundamental challenge facing them.

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Enhancing eFPGA Functionality with Speedcore Custom Blocks (WP009)

Achronix Speedcore™ eFPGA IP can be integrated in an SoC for high-performance, compute-intensive and realtime processing applications such as AI, automotive sensor fusion, network acceleration and wireless 5G. Speedcore eFPGA IP is a game-changer for SoC developers, allowing them to add flexibility to their products by including FPGA technology in their ASICs. For SoC development, companies specify the quantity and mix of lookup-table (LUT) logic, embedded memory blocks, and DSP blocks that best meets their needs. Along with these functions, Achronix now offers the ability for companies to define custom block functions, optimized for their application, that can also be included in the eFPGA fabric. Speedcore custom blocks increase die area efficiency, increase performance and lower power.

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Evaluating Speedcore IP For Your ASIC (WP007)

Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues.

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FPGAs and eFPGAs Accelerate ML Inference at the Edge (WP026)

With the rapid proliferation of Internet-of-Things (IoT) and billions of connected devices, there is a paradigm shift taking place where big data is not only being processed in the core data center but also at the network edge. Field Programmable Gate Arrays (FPGAs), sitting at the intersection of performance and flexibility, are a promising solution for deep learning edge inference applications.

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FPGAs Enable the Next Generation of Communication and Networking Solutions (WP021)

Communications and networking systems that extend from the edges of the 5G network to the switches inside data centers are placing extreme pressure on the ability of silicon to support the computational and data-transfer rates they require. Traditionally programmable logic provided the best mixture of flexibility and speed for these systems, but has been challenged in recent years by the increase in speed. Through the inclusion of an innovative, multilevel network on chip that allows data to be streamed easily around the device without impacting the FPGA fabric, the Speedster7t architecture ensures all device resources are used to their full potential.

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Title Description Version Released Date Document File
Repeatability in ACE (AN012)

One of the desired requirements of any FPGA design tool is the ability to reproduce the exact same results every time the tool is run under the same conditions — a requirement refereed to as repeatability. The ACE placer and router are deterministic, delivering 100% repeatability.

1.2 Repeatability_in_ACE_AN012.pdf
Routing Reset Signals on Speedcore eFPGAs (AN007)

In FPGA design, reset signals can sometimes have a significant effect on the overall quality of timing or routing results. Generally it is recommended to reduce the number of logic elements that need to be reset by taking advantage of initial values and coding in such a way that reset is only needed on a few end points.

1.2 Routing_Reset_Signals_on_Speedcore_eFPGAs_AN007.pdf
Runtime Programming of Speedster FPGAs (AN025)

This application note demonstrates changing the I/O ring configuration registers of a Speedster FPGA while in user mode.

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SoC-Speedcore Interface Tests (AN022)

The input and output paths between the host SoC and a Speedcore instance are an important test component. It is essential to have a structure that ties seamlessly to the SoC's test flow without requiring special functions such as loading a bitstream in the Speedcore instance.

1.0 SoC-Speedcore_Interface_Tests_AN022.pdf
Speedcore User Interface Timing Sign-off Methodology (AN009)

Timing sign-off between the host ASIC and the Speedcore boundary is one of the most crucial steps in ensuring proper integration of a Speedcore instance into a customer's SoC.

1.1 Speedcore_User_Interface_Timing_Sign-off_Methodology_AN009.pdf
Title Description Version Released Date Document File
Speedcore Configuration User Guide (UG061)

During normal SoC operation, the Speedcore eFPGA core requires configuration by the end user. This guide covers the details of how to configure a Speedcore instance via JTAG, CPU, or serial flash interface. Also included are details on the Achronix Configuration Bus (ACB) interface that can be used to program configuration bits for ASIC IP surrounding the Speedcore eFPGA.

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Speedcore DFT and Test User Guide (UG067)

Design for test (DFT) is an important consideration for Speedcore eFPGAs from the perspective of both Achronix and the ASIC integrator. The programmable nature of Speedcore eFPGAs deliver the inherent benefit of being able to use the programmable logic fabric to test itself. This guide describes Speedcore eFPGAs from a testability perspective and outlines the general features and methodologies that Achronix uses to achieve the necessary coverage.

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Speedcore Power Estimator User Guide (UG073)

The Achronix Speedcore Power Estimator tool provides a platform to calculate the power requirements for Achronix Speedcore eFPGAs. This user guide gives a detailed overview of the thermal and power needs depending on the device, environment and utilization of components in the design.

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Speedcore Power User Guide (UG066)

The power user guide covers the Achronix default power and signal integrity sign-off methodology with all relevant sign-off conditions. Also covered are power rail integration guidelines, power supply sequencing, power-on reset, and ESD guidelines.

1.8 Download
Speedcore Software Integration and Flow User Guide (UG062)

Speedcore Software Integration and Flow User Guide (UG062)

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