Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)

Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. Achronix's solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family.

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FPGAs Enable the Next Generation of Communication and Networking Solutions (WP021)

Communications and networking systems that extend from the edges of the 5G network to the switches inside data centers are placing extreme pressure on the ability of silicon to support the computational and data-transfer rates they require. Traditionally programmable logic provided the best mixture of flexibility and speed for these systems, but has been challenged in recent years by the increase in speed. Through the inclusion of an innovative, multilevel network on chip that allows data to be streamed easily around the device without impacting the FPGA fabric, the Speedster7t architecture ensures all device resources are used to their full potential.

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FPGAs for Advanced Video Processing Solutions (WP022)

While the performance of an ASIC is typically high enough for broadcast-quality video processing, it supports only the feature set conceived of at design time and is not field upgradable. A CPU is the most flexible and easiest to design; however, clock frequencies have plateaued, and the era of dramatic improvements in performance are over. FPGAs represent a good balance between performance and flexibility for this class of applications.

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The AI Evolution Calls for Adaptable Inferencing Platforms (WP023)

Deep learning's demand for computing power is growing at an incredible rate, accelerating recently from doubling every year to doubling every three months. Increasing the capacity of deep neural network (DNN) models has shown improvements across a wide range of areas ranging from natural language processing to image processing. This growth calls for the adoption of customized architectures that squeeze the greatest amount of performance out of each transistor available.

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An FPGA-Based Solution for a Graph Neural Network Accelerator (WP024)

Thanks to the rise of big data and the rapid increase in computing power, machine learning technology has experienced revolutionary development in recent years. Machine learning tasks such as image classification, speech recognition, and natural language processing, operate on Euclidean data with a certain size, dimension, and an orderly arrangement. However, in many realistic scenarios, data is represented by complex non-Euclidean data such as graphs. In this context, many new graph-based machine learning algorithm, or graph neural networks (GNNs), are constantly emerging in academia and industry.

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Title Description Version Released Date Document File
Speedcore User Interface Timing Sign-off Methodology (AN009)

Timing sign-off between the host ASIC and the Speedcore boundary is one of the most crucial steps in ensuring proper integration of a Speedcore instance into a customer's SoC.

1.1 Speedcore_User_Interface_Timing_Sign-off_Methodology_AN009.pdf
Understanding ACE Timing Reports (AN024)

Accurate timing constraints and proper understanding of timing analysis reports are critical to successful FPGA design projects. This application note introduces ACE users to the structure of ACE timing reports generated during an ACE place-and-route run.

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Runtime Programming of Speedster FPGAs (AN025)

This application note demonstrates changing the I/O ring configuration registers of a Speedster FPGA while in user mode.

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Coding Guidelines for Speedcore eFPGAs (AN003)

This application note details certain specific design elements that, with certain coding constructs and constraints, can improve timing performance or lower resource utilization.

2.1 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Migrating to Achronix FPGA Technology (AN023)

Many users transitioning to Achronix FPGA technology are familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences is necessary to achieving the very best performance and quality of results (QoR).

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Title Description Version Released Date Document File
Speedcore ASIC Integration and Timing User Guide (UG064)

This guide details the design flow for integrating a Speedcore eFPGA into an ASIC, including closing timing across the boundary between the Speedcore instance and the surrounding host ASIC, along with how to perform full-chip simulation.

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Speedster7t Power Estimator User Guide (UG093)

The Achronix Speedster7t Power Estimator tool provides a platform to calculate the power requirements for the Achronix 7nm standalone FPGAs. This user guide gives a detailed overview of the thermal and power needs depending on the device, environment and utilization of components in the design.

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Speedster7t AC7t1500 Board Designers Guide (UG101)

The Speedster7t AC7t1500 FPGA includes several advanced interfaces that require careful design in order to operate at their peak performance. This guide is intended as a general overview of PCB design principles that help the designer get the most out of the AC7t1500 FPGA. This guide is broken down by system components. These include the Ethernet, the PCIe5, the GDDR6 memory and the DDR4 memory interfaces.

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Speedster7t Component Library User Guide (UG086)

The Achronix Speedster7t component library provides the user with building blocks that may be instantiated into the user’s design. These components provide access to low-level fabric primitives, complex I/O blocks, and higher level design components. Each library element entry describes the operation of the component as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.

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Speedster7t Power User Guide (UG087)

This document describes the different power supplies that are required for the Speedster7t 7t1500 device and voltage tolerance levels for each of them. Also included are the connection guidelines for each of the power rails and recommendations for the power supply network sharing schemes at the board level.

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