Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
An FPGA-Based Solution for a Graph Neural Network Accelerator (WP024)

Thanks to the rise of big data and the rapid increase in computing power, machine learning technology has experienced revolutionary development in recent years. Machine learning tasks such as image classification, speech recognition, and natural language processing, operate on Euclidean data with a certain size, dimension, and an orderly arrangement. However, in many realistic scenarios, data is represented by complex non-Euclidean data such as graphs. In this context, many new graph-based machine learning algorithm, or graph neural networks (GNNs), are constantly emerging in academia and industry.

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Data Orchestration Supports the Next Advance in AI (WP025)

Artificial intelligence (AI) and machine learning (ML) technologies now power a rapidly expanding range of product and applications from deeply embedded systems to hyperscale data-center deployments. Although there is a huge degree of diversity in the hardware designs supporting these applications, all require hardware acceleration. Data orchestration encompasses the pre- and post-processing operations that ensure the data seen by a machine learning engine arrives at an optimal speed and in the most suitable form for efficient processing.

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EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)

The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies.

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Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)

Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. Achronix's solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family.

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Embedded FPGA – a New System-Level Programming Paradigm (WP006)

The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order.

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Title Description Version Released Date Document File
Measuring Accurate Toggle Rates

When calculating dynamic power for a design, one input to any power estimation is the toggle rate of the signals. In most circumstances, the value used will be one of the industry standards of either 12.5% or 25% — values derived from a wide range of designs.

1.0 Measuring_Accurate_Toggle_Rates_AN010.pdf
Migrating to Achronix eFPGA Technology (AN014)

Many users transitioning to Achronix eFPGA technology will be familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences are needed to achieve the very best performance and quality of results (QoR).

1.1 Migrating_to_Achronix_eFPGA_Technology_AN014.pdf
Migrating to Achronix FPGA Technology (AN023)

Many users transitioning to Achronix FPGA technology are familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences is necessary to achieving the very best performance and quality of results (QoR).

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PCIe Enumeration of Speedster7t FPGAs (AN027)

This Application Note provides the steps to attain enumeration from a non-enumerated device with a PCIe interface and from an already enumerated device.

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Pipelining the CPU Interface (AN016)

A Speedcore instance hosted in an SoC supports three different configuration modes: CPU, serial flash and JTAG. In CPU mode, an external CPU acts as the master and controls the programming operations for the Speedcore eFPGA, and offers a high-speed method for loading configuration data.

1.0 Pipelining_the_CPU_Interface_AN016.pdf
Title Description Version Released Date Document File
Real-Time ASR Accelerator for Data Centers (PB036)

A real-time automatic speech recognition (ASR) accelerator for data centers, featuring industry-leading WER, concurrent real-time streams, and lowest latency — all running on a single VectorPath accelerator card.

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Speedcore eFPGA Product Brief (PB028)

Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.

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Speedcore eFPGA Test Chip Evaluation Board (PB030)

The Speedcore eFPGA evaluation board from Achronix contains the 16-nm Speedcore eFPGA test chip. The evaluation board’s Speedcore test chip has been customized with the right blend of resources such as LUTs, BRAMs, DSP64s, DFFs and a number of I/O so as to provide an optimum programmable platform for demonstrating, evaluating and testing Achronix’s Speedcore technology.

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Speedster7t FPGAs Product Brief (PB033)

The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.

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VectorPath S7t-VG6 Accelerator Card

Developed jointly with BittWare, the VectorPath® S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications.

2023.06.05 Download
Title Description Version Released Date Document File
Snapshot User Guide (UG016)

Snapshot is the real-time design debugging tool for Achronix FPGAs and cores. This guide details the setup and operation of the Snapshot feature using a simple reference design.

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Software Development Kit User Guide (UG107)

This Guide introduces the Achronix Software Development Kit and details each of the provided structures and functions.

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Speedcore ASIC Integration and Timing User Guide (UG064)

This guide details the design flow for integrating a Speedcore eFPGA into an ASIC, including closing timing across the boundary between the Speedcore instance and the surrounding host ASIC, along with how to perform full-chip simulation.

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Speedcore Clock and Reset Architecture User Guide (UG063)

This user guide details the clock structure for a Speedcore instance, covering the global core clock network, and interface clock networks. This guide also covers various clocking scenarios and their impact on timing closure.

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Speedcore Component Library User Guide (UG065)

This library describes the programmable fabric silicon elements which may be instantiated into a custom design.

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