Speedster®22i devices contain up to six embedded DDR3 controllers which can be used to interface with and control off-chip DDR3 memory devices or DIMMs. Each of the DDR controllers supports up to 72-bit wide data up to 1866 Mbps (933 MHz DDR).
The DDR3 controller supports both “auto” and “custom” modes. When in the “auto” mode, functions such as (but not limited to) activating/precharging banks/rows, running calibration algorithms, and initialization sequences are handled transparently to the user by the embedded DDR controller. The mapping of byte lanes to pins is handled transparently by the embedded DDR PHY. When in “custom” mode the user has the option to manually override functions such as automated refresh and initialization engines/sequences.
- 1866 Mbps data rate
- The controller and PHY run up to 933 MHz
- To achieve 1866 Mbps data rates, a 2x clock setting must be enabled, allowing the logic fabric to operate at half rate speed (467 MHz). The 2× clock setting can be enabled regardless of the data rate, allowing the interface to the fabric to run at half the rate of the hard IP controller.
- 8:1 DQ:DQS ratio
- Each controller supports eight DQ signals for every DQS
- Four chip selects (ranks) per controller
- The external memory connected to each controller can be comprised of up to four ranks (either four single-rank DIMMs or two dual-rank DIMMs)
- Registered DIMM and unbuffered DIMM support
- Each controller can independently support either rDIMMs or uDIMMs
- Address mirroring is supported
Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10 Gbps to 100 Gbps and beyond. Using the latest SerDes technology and a flexible protocol layer, Interlaken minimizes the pin and power overhead of chip-to-chip interconnect and provides a scalable solution that can be used throughout an entire system. One of the main benefits of Interlaken is its scalability and flexibility to accommodate different system designs.
Speedster22i devices include a high-performance, low-power and flexible implementation of the Interlaken protocol. The core is compliant with the Interlaken protocol definition, revision 1.1, and offers a fast, turnkey Interlaken interface for chip-to-chip interconnect.
The Interlaken hardened IP can be configured in any of the following configurations:
The SerDes speed is variable from 4.6 Gbps to 10.325 Gbps when configured to use the Interlaken protocol.
The Speedster22i PCI Express hard IP cores implement all three layers (physical, data link, and transaction) defined by the PCI Express standard.
- PCI Express base specification revision 3.0 version 0.9 compliant; backward compatible with PCI Express 2.1/2.0/1.1/1.0a
- ×1, ×4 or ×8 PCI Express lanes
- 8.0 GT/s, 5.0 GT/s, and 2.5 GT/s line rate support
- Operates as endpoint only
- PIPE-compatible PHY interface
- Support for autonomous and software-controlled equalization
- DMA engine
Speedster22i devices contain up to four independent, embedded Ethernet MACs. Having these functions as hard IP in Speedster22i FPGAs provides significant power savings and reduces design complexity.
The 10/40/100 gigabit Ethernet MAC and PCS IP is designed to comply with the IEEE P802.3ba specification draft 2.2. The IP can be used in either NIC (Network Interface Card) or Ethernet switching applications. A set of configuration registers is available to dynamically set the IP to terminate and form MAC frames (NIC application) or to pass MAC frames without modification to the user application or to the Ethernet line (switching application). When used in NIC or switching applications, the IP provides support for IEEE managed objects, IETF MIBII and RMON for management applications (e.g. SNMP).
The Channelized MAC and PCS core can be configured to support either one of the following configurations:
- 1 12 × 10 gigabit Ethernet channels
- 1 × 100 gigabit, 1 2 × 10 gigabit Ethernet channels
- 1 3 × 40 gigabit Ethernet channels
- 1 4 × 10 gigabit, 1 2 × 40 gigabit Ethernet channels
- 1 8 × 10 gigabit, 1 × 40 gigabit Ethernet channels