The networking telecommunication world is continuing its decades-long evolution toward higher data rates, higher traffic volume, a more diverse mix of traffic types, and packet-based protocols, with an overlay of connection-based mechanisms.



This capability results from the deployment of high-speed SerDes transceivers as independent lanes, rather than as grouped clusters sharing clocking functions. With Speedster22i devices, a line card can be provisioned with diverse line types, and an interface can be changed in operational mode without disrupting other traffic.



  • Substantial data path bandwidth for high traffic volume
  • Substantial external memory capacity for traffic buffering
  • Substantial external memory bandwidth
  • Substantial login capacity to implement complex queuing algorithms
  • Substantial internal memory for queuing pointers, policy tables and scratchpad RAM

Provided by Speedster22i FPGAs:

  • Up to 200 Gigabit Ethernet and 200 Gigabit Interlaken
  • Up to six independent DDR3 ×72 interfaces at 1600 Mbps
  • Up to 691 Gbps of raw memory bandwidth
  • Up to 1 million effective LUTs
  • Up to 86 Mb of internal SRAM

Speedster22i devices contain hard IP blocks for the interfaces described above. These fully-hardened IP blocks provide the following benefits:

  • Consume no programmable resources (LUTs, memory and routing)
  • Require no timing-closure (timing guaranteed by design)
  • Consume less power
  • Contribute less latency
  • Require no license fees
  • Fully bypassable, so that I/O and SerDes lanes can be freely used for other purposes

The hard-wired nature of the embedded hard IP protocol blocks leaves more programmable logic capacity, which can be used for additional functions, including;

  • Packet forwarding/classification into distinct flows for QoS guarantees
  • Tables updates (routing QoS policy)
  • Oversubscription management statistics gathering
  • Traffic management (policing, queuing, scheduling and shaping)
  • Other functions like compression/decompression, encryption/decryption and error detection/correction

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