(6200-1030) Senior Staff Engineer

Job Title

(6200-1030) Senior Staff Engineer

Hardware Engineering (US)
Santa Clara, CA
Job Description

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.

Position Profile Name:Senior Staff Engineer

Requisition No.:6200-1030

Type of Position:Regular, Exempt

Reports to:Manager, Hardware Engineering


Hardware Engineering (US)


Santa Clara, CA


Job Description

The successful candidate will join the Hardware Engineering group in Santa Clara, US. This is an exciting position that provides the opportunity to lead the hardware design development for all validation and reference design PCBs for Achronix’s product lines and test chip designs. The employee should be self-driven, constantly looking to set the bar higher, and a driver of excellence.


The primary responsibilities for this position are:

  • Hardware design of Validation PCBs for Achronix’s high end FPGA products
  • Understand the product PRD and plan the development of PCBs needed to validate Achronix’s FPGA products
  • Design of next generation FPGA development boards supporting high end SerDes, GDDR6, DDR5 etc.
  • Development of FPGA validation hardware
  • Implement configurable I/O modules on Hardware for high speed interfaces
  • Design high-speed SerDes interface boards and adaptors
  • Generate technical specifications, reference designs and app notes for customers
  • Development of DDR5/GDDR6 interface hardware with backward compatibility and future expansions
  • Hardware bring up for validation
  • PCB Characterization and testing
  • PHY I/O validation and compliance testing
  • Communicate technical challenges and drive for improvement
  • Perform basic signal integrity analysis at PCB level
  • Work on pre-layout to post-layout execution of the given interface at package and system level
  • Provide detailed guidelines to customers on board design and layout
  • Participate in team meetings and occasionally with global teams
  • Hardware, Systems, Software Product planning and Application Engineering
Required Skills
  • Experience working with Schematics of high-speed interfaces
  • Experience working with PCIe/DDR/Ethernet etc.
  • Experience with Electrical test and characterization of silicon test chips in a lab environment
  • Thorough knowledge of related Lab equipment
  • Capable of independently understanding standard specifications of PCIe/DDR/GDDR/JEDEC and transfer to product requirements for hardware implementation
  • Experience with Cadence PCB design and layout tools
  • Strong problem-solving skills
  • Full understanding of SOC digital design methodology/FPGA
  • Previous experience designing at least 8-10 high speed PCBs
  • Ability to work and communicate with Global teams
  • Intrinsically driven, and always raising the bar
  • Ability to take high-level requirements and create solutions around those
  • Thrives in a dynamic and fast-paced environment with a pro-active mindset
  • Works well with other team members and has a collaborative approach
  • Power integrity and signal integrity fundamentals
Education and Experience
  • B.E in Electronics/Electrical with 12+ years of overall experience or M.S. with 10+ years of experience