(6200-1029) Senior Engineer

Job Title

(6200-1029) Senior Engineer

Department
Hardware Engineering (US)
Location
Santa Clara, CA
Job Description

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.

Position Profile Name:Senior Engineer

Requisition No.:6200-1029

Type of Position:Regular, Exempt

Reports to:Manager, Hardware Engineering

Department:

Hardware Engineering (US)

Location:Santa Clara, CA

Contact:hr@achronix.com

Job Description/Responsibilities

This is an exciting position in the Hardware Engineering group in Santa Clara, US, offering exposure to driving customer solutions on PCB design, layout and SI/PI. The successful candidate should be self-driven, constantly looking to set the bar higher, and a driver of excellence.

Responsibilities include the following:
  • Address customer queries on PCB schematics, layout and SI/PI
  • Help customers design PCBs/systems with Achronix’s FPGA products
  • Generate technical specs, reference designs and app notes for customers
  • Participate in internal product PCB package and PCB development
  • Provide detailed guidelines to customers on board design and layout
  • Provide guidelines to customers, Hardware design of Validation PCBs for Achronix’s high end FPGA products

  • Interact with internal teams and IP partners to resolve customer issues, perform basic signal integrity analysis at PCB level

  • Provide layout design support to customers

  • Help customers with generating SI/PI methodologies for validating systems with Achronix’s FPGA products

  • Review customer's SI/PI simulation results and provide a go/no go on PCB design performance

  • Participate in team meetings and occasionally with global teams spanning Hardware, Systems, Software Product planning and Application Engineering

Required Skills
  • B.E with Electronics/Electrical with 6+ years of overall experience or M.S. with 4+ years of experience
  • Experience working with Schematics of high speed interfaces
  • Experienced in layout review and providing feedback for improvement
  • Experienced in layout model extraction and SI simulations
  • Experience working with PCIe/DDR/Ethernet and other interfaces
  • Capable of independently understanding standard specifications of PCIe/DDR/GDDR/JEDEC and transfer into product requirements for hardware implementation
  • Experience with Cadence PCB design and layout tools
  • Strong problem-solving skills
  • Full understanding of SOC digital design methodology/FPGA
  • Ability to work and communicate with Global teams
  • Intrinsically driven, and always raising the bar
  • Ability to take high-level requirements and create solutions around them
  • Thrive in a dynamic and fast-paced environment, with a proactive mindset
  • Work well with other team members using a collaborative approach