Design Engineer Intern (6500-1011)

Job Title

Design Engineer Intern (6500-1011)

Department
Architecture
Location
Santa Clara, CA

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.

Position Profile Name:Design Engineer Intern (PCIe / NoC Device Bringup & Characterization)

Requisition No.:6500-1011

Type of Position:Regular, Exempt

Reports to:VP Architecture

Location:Santa Clara, California

Contact:hr@achronix.com

 

Job Description/Responsibilities

Under the guidance of a Sr. Engineer, the employee will contribute to the , testing, and characterization of new devices with an initial focus on the Speedster 7t1500 NoC and/or PCIe interfaces. 

Required Skills
  • Excellent communication skills (verbal and written)
  • Ability to handle multiple tasks
  • Demonstrated understanding of engineering fundamentals and technical analytical skills
  • Ability to establish and sustain positive relationships with extended teams
  • Excellent communication skills (verbal and written)
Technical Skills
  • Logic Design, Computer Architecture
  • Test Equipment
  • FPGA design
  • PCIe, On Chip Networks, AXI
Education and Experience
  • A minimum of 5+ years experience.
  • Bachelor or Master’s degree in Computer or Electrical Engineering.