Verification Engineer, Memory Protocols (6400-1038)

Job Title

Verification Engineer, Memory Protocols (6400-1038)

Hardware Engineering
Bangalore, India

The Hardware Engineering group in India is responsible for all SoC hardware and package design at Achronix. It develops and integrates high-speed serial and parallel interface PHYs and controllers, network-on-chip, clocking & reset, etc. The Hardware Engineering group is hiring a Staff Engineer, who will be responsible for the verification of various memory IP and GPIO subsystems. The employee will write verification plans, develop the testbenches and create the tests for one or more memory IP subsystems, including DDR4/5, GDDR6, HBM2/3, as well as GPIO subsystems. The employee may also contribute to common/generic methodology and testbench architecture or other subsystems.

The employee should be self-driven, constantly looking to set the bar higher, and a driver of excellence.

The employee should have a strong knowledge of memory protocols, and should have experience with developing verification plans from scratch, creating testbench architectures, coverage analysis, etc.

The employee’s responsibilities will include the following:

  • Write the verification plan for one or more subsystems
  • Develop the testbench and tests for one or more subsystems
  • Track coverage and ensure high quality verification
  • Review microarchitectures for various subsystems
  • Work with RTL designer on failure debug
  • Drive methodologies and best practices across all SoC verification
  • Post-Si validation support
  • Participate in meetings with local and global teams spanning Hardware, Systems, Software & Product Engineering
Required Skills
  • Expertise in verification of at least one memory interface, like DDR4/5, GDDR6, HBM2e/3, etc.
  • Strong background in AMBA standards, especially AXI4/5 and APB
  • Strong UVM knowledge
  • Excellent written and verbal communication skills
  • Intrinsically driven, and always raising the bar
  • Ability to take high-level requirements, and create solutions around those. Must be able to see the big picture
  • Experience with post-Si bring-up & debug
  • Thrives in a dynamic & fast-paced environment, with a pro-active mindset
  • Works well with other team members and has a collaborative approach
  • Expertise in performance modeling, or a background in system-level performance test creation is a big plus
  • Experience with emulation is a plus
  • Automation & scripting experience, especially in Python and/or Perl is a plus
Education and Experience
  • BS or MS and 6+ years of experience
  • Previous experience in at least 2-3 product developments, potentially including post-Si bring-up