Hardware Engineer-Physical Design (6200-1022)

Job Title

Hardware Engineer-Physical Design (6200-1022)

Department
Hardware Engineering
Location
Santa Clara, CA

Achronix Semiconductor is a fabless semiconductor corporation based in Santa Clara, California.  We design high-performance, low-power FPGAs using advanced process node technologies.

Achronix is currently shipping its 22nm HD1000 FPGA, making us the only customer of Intel’s custom foundry program to ship product, as well as the FPGA industry’s process-technology leader.

The Core Technology team at Achronix owns the reconfigurable “fabric” (look-up tables, routing, configuration memory, carry chains, register files, multipliers, etc.) for our company’s FPGAs.  Members of our team participate in all phases of the FPGA product-development cycle, from architecture conception to circuit design and implementation to high-volume manufacturing.  New employees will have the opportunity to contribute to all of these phases and work with the world’s most advanced process technology.

The employee will work on the Physical Implementation of blocks from RTL to GDS in advanced FinFet technology nodes (7nm/12nm/14nm/16nm) and below. The employee will share responsibilities across design and verification. His or her responsibilities will include the following:

 

 

  • RTL Synthesis, writing Timing, Area, and other relevant constraints.
  • Floorplanning, Power Grid implementation, Clock Tree Synthesis, Place and Route.
  • Parasitic extraction and Physical Design verification.
  • Static timing analysis, and timing closure.
  • Lint, Design for Test, Test Coverage.
  • EM/IR verification and logic equivalence/formal verification.
  • Low Power design and power optimization.
  • Collaborate with other members of the team to optimize design in context.
  • Work with other team members to improve methodologies and flows.
  • Support post-silicon product bring-up and debug, timing and power characterization.

 

Skills and Qualifications:

  • Experience with digital VLSI CMOS circuit design and physical design in advanced FinFet technology nodes.
  • Experience with Hardware Description Languages like Verilog.
  • Experience with Industry standard tools like Design Compiler, ICC2, PrimeTime, Tetramax, RedHawk, ICV, Caliber LVS/DRC.
  • Excellent debugging skills.
  • Comfortable programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch (e.g. 5000+ lines of code).
  • Familiarity with revision-control systems (e.g., perforce, git).
  • Familiarity with using and/or designing FPGAs is a plus.
  • Well organized, punctual, excellent communication skills, ability to operate without direct supervision, ability to collaborate with other team members.
  • MS in Electrical Engineering with +2-10 years experience.