Sr. Digital Design Engineer (6500-1004)
Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.
Achronix is seeking a talented and self-driven Digital Design Engineer to join our Architecture and Design team developing the next generation FPGA. In this role, candidates will design a portfolio of NOCs, subsystems, and IP in the latest technology nodes.Primary Job Responsibilities
The primary responsibilities for this position are:
- Responsible for SoC Frontend Architecture and Design. Define micro-architecture specifications.
- RTL coding using SystemVerilog and/or Verilog. Explore system latency, bandwidth, area, and power tradeoffs. Identify bottlenecks and propose solutions.
- Implement and integrate high-speed interfaces.
- Implement and integrate low-latency and high-performance subsystems.
- Perform feasibility study on different third party IP and NOCs to integrate IP at the SOC level.
- Closely work with Verification team and help define test plan. Run tests and debug design.
- Lead the performance model development. Participate in design reviews of hardware systems and related software systems.
- Run Lint, CDC, Synthesis, STA and formal verification tools. Work closely with Backend team on floorplan, Constraints definition and timing analysis.
- Support FPGA prototyping and post-silicon system bring-up.
- Collaborate with internal and external team members on architectural decisions, development flows and methodologies.
- Hands-on experience with NoC design and integration with interconnect protocols, such as AXI, ACE, APB, etc.
- Expert RTL developer with SystemVerilog experience, using ASIC development techniques and designs flows at modern technology nodes, including synthesis and timing closure.
- Strong Python coding skills.
- Strong knowledge in digital design that involves multiple clock domains, clock power management.
- Knowledge of low speed system peripheral bus.
- Knowledge of low power design, tools and methodologies. Power intent UPF specifications knowledge a plus.
- Excellent communication and documentation skills.
- A minimum of 5+ years experience in SOC/ASIC Front-End design
- Bachelor or Master’s degree in Computer or Electrical Engineering