(6500-1029) Staff RTL Design & Architecture Engineer

Job Title
(6500-1029) Staff RTL Design & Architecture Engineer
Santa Clara, CA
Job Description

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. The Achronix FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All Achronix products are supported by best-in-class EDA software tools.

Job Description/Responsibilities

The successful candidate will lead and contribute to the Architecture, design, verification and silicon validation of high-performance SoCs

Primary Job Responsibilities

  • Responsible for SoC front end architecture and design, defining microarchitecture specifications
  • Perform RTL coding using SystemVerilog and/or Verilog. Perform feasibility study on different third party IP and integrate IP at the SoC level
  • Develop IP. Work closely with verification team and help define test plan, run tests and debug designs
  • Lead the performance model development. Participate in design reviews of hardware systems and related software systems
  • Run Lint, CDC, Synthesis, STA and formal verification tools. Work closely with backend team on floorplan, constraints definition and timing analysis
  • Support FPGA prototyping and post-silicon system bring-up
  • Collaborate with internal and external team members on architectural decisions, development flows and methodologies

Required Skills

  • Expert RTL developer having experience with SystemVerilog, ASIC techniques and design flows, including synthesis and timing closure
  • Excellent communication and documentation skills
  • Experience with one or more of the following technology areas:
    • High speed I/O and SerDes
    • Ethernet, including high-speed links (100 Gbps+) and priority-based flow control (PFC)
    • NoC design SoC protocols, such as CHI, AXI, ACE, APB, etc.
    • CPU microarchitecture (e.g., x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems
    • Inter-device protocols (e.g., PCIe, CXL)
  • Experience with one or more industry standard (or proprietary) interconnect technologies (e.g., AMBA, CHI, CCIX, CXL, etc.)
  • Post-silicon validation and debug experience
  • FPGA design experience is a plus
  • Knowledge of low-power design, tools and methodologies, including power intent UPF specifications, a plus

Education and Experience

  • BS with 8+ years of experience or MS with 6+ years of experience or PhD with 3+ years of experience in Electrical Engineering, Computer Engineer or related equivalent
  • At least 5 years of RTL design experience related to SOC/ASIC design

The compensation range for this position is $160,000–$200,000. Salary ranges dependent on experience and location.