The employee will drive the functional verification of FPGA core IP components and surrounding logic in high-performance FPGA devices at 16nm/7nm and below. His or her responsibilities will include the following:
- Drive functional verification of core IP components and embedded FPGA integration.
- Planning and execution of verification suite, including DSP IP, machine learning IP, memory IP, and synthesis accuracy.
- Interact with design and software development groups in device-level and board-level verification.
- Architecture, detailed design, coding, bring-up, testing, performance measurement/demonstration and delivery of example test benches for customers.
- Support overall product bring-up by executing test vectors in hardware using FPGA core.
- Contribute to creation of hardware test vectors.
- Knowledge and familiarity with modern verification techniques, such as SystemVerilog directed test benches and constrained random verification. Knowledge of UVM is preferred.
- Ability to write complex test and verification plans.
- Experience verifying highly parameterizeable IP a plus.
- Experience with computer mathematics such as IEEE754 floating point a plus.
- Experience with modern interfaces and protocol such as PCI Express and DDR a plus.
- Strong in technical writing and communication (verbal) skills
Education and Experience
- A minimum of 3+ years experience.
- Bachelor or Master’s degree in Computer or Electrical Engineering.
Verification Engineer (6410-1005)
Type of Position
Sr. Director, Systems Engineering
Santa Clara, California