Lead Engineer/Manager for Memory Subsystems (6400-1041)

Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix's history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

The India Technology Center leads all SoC development at Achronix Semiconductor, working on end-to-end design development, from architecture development all the way to chip tape-out for Achronix’s Speedster and Speedcore class of FPGAs. The team owns the design of various high-speed SerDes, memory and NoC architecture subsystems, maximizing the data bandwidth and latency in and out of Achronix FPGAs.

Job Description/Responsibilities

The opening is for a design lead who is responsible for the entire design and execution of various memory and GPIO subsystems, leading a cross-functional team across RTL, verification, DFT and physical design. This employee is expected to provide technical leadership to their team and be the go-to engineering expert on memory protocols. The primary responsibilities include:

  • Plan and manage the execution of the multiple subsystems, tracking interactions and hand-offs between different team members
  • Provide technical leadership to the team, especially on protocol-specific design decisions and priorities
  • Interface with various teams, including architecture, planning, software, packaging and product engineering, to align on specs, PRDs and hand-offs across teams
  • Interface with the various technical horizontals to ensure flows are being used correctly and various QA reviews are being conducted
  • Interface with third-party IP vendors on various technical issues

Required Skills

  • Expertise in memory controllers and PHYs, especially DDR4/5, GDDR6 and HBM2/2e
  • Experience with interconnect protocols, such as AXI, ACE, APB, etc.
  • Good knowledge of various simpler GPIO protocols, such as I2C, SPI, etc.
  • Excellent verbal and written communication skills
  • Ability to work in a dynamic and fast-paced environment, with a proactive mindset
  • Experience with post-Si bring-up and debug
  • Experience with system-level performance modeling is a plus
  • Experience with PCIe/CXL/CCIX is a plus
  • Experience with synthesis and STA is a plus

Education and Experience

  • BS/MS with 9+ years of experience, the significant part of which is in memory PHY and/or controller design and verification
  • Prior experience leading cross-functional teams
  • Worked on designs at the latest process nodes
  • Previous experience on at least 3-4 product developments, preferably including post-Si bring-up

Job Details

Job Title
Lead Engineer/Manager for Memory Subsystems (6400-1041)
Requisition No
Type of Position
Full Time
Reports To
Sr. Director, India Technology Center
Bangalore, India
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