IP Verification Manager, Systems (6410-1004)

Job Description/Responsibilities

The employee will lead the System Engineering team's functional verification and validation of FPGA hard and soft IP components and surrounding logic in high-performance FPGAs at 16nm/7nm and below. His or her responsibilities will include the following: 

• Lead functional verification of hard (ASIC) IP component developed by the Systems Engineering IP team.
• Lead functional verification of soft (FPGA) IP components delivered to customers as part of our IP library.
• Develop verification methodologies that can support highly configurable hard and soft IP components.
• Planning and execution of verification suite, including DSP, machine learning, and memory IP with a focus on synthesis accuracy.
• Contribute to the bring-up and validation of Achronix silicon devices.
• Interact with design and software development groups in device-level and board-level verification.
• Contribute to creation of hardware test vectors (ATE vectors).

Required Skills

• Expertise with with modern verification techniques, including UVM, SystemVerilog directed test benches, and constrained random verification. 
• Ability to write complex test and verification plans.
• Strong leadership and organizational skills.
• Experience verifying highly parameterizeable IP a plus.
• Experience with computer mathematics such as IEEE754 floating point a plus.
• Experience with modern interfaces and protocol such as PCI Express, Ethernet, and DDR a plus.
• Strong in technical writing and communication (verbal) skills

Education and Experience

• A minimum of 10+ years’ experience.
• Bachelor or Master’s degree in Computer or Electrical Engineering.