Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix's history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

Title: Staff Engineer
Requisition No.: 6400-1031
Type of Position: Regular, Exempt
Reports to: Sr. Director, India Technology Centre
Location: Bangalore, India
Contact: hr@achronix.com

Job Description/Responsibilities

Primary Responsibilities:

The employee needs to have a holistic understanding of timing analysis. The employee will be responsible for STA methodology development, constraints generation and management, and full chip-level STA sign-off. The employee is also expected to have very strong scripting skills and knowledge in order to create methodologies and automations for FPGA specific library generation. Specific responsibilities include:

  • Develop ASIC STA methodology and flows
  • Work with other stakeholders to drive STA sign-off methodologies across the company and work especially closely with the software team
  • Own block-level and/or full chip STA runs and sign-off
  • Co-own methodology for delay extraction and handshake between software and hardware
  • Work with other ASIC engineers in both front-end and back-end design on all aspects specific to STA
  • Work with EDA partners to ensure that Achronix is using the best methodologies and that the EDA partners are providing the adequate level of support

Skills:

  • Very strong background in STA methodology and flows
  • Experience with STA flow and sign-off requirements for ?20nm nodes
  • Very good understanding of process technology and implications on STA sign-off conditions
  • Very strong in automation development and scripting. Good knowledge of Tcl, Perl/Python, and data structures
  • Strong ASIC design background
  • Experience with post-Si bring-up and performance correlation against pre-Si STA sign-off is a plus
  • Background in EDA algorithms is a plus
  • Excellent verbal and written communication skills

Experience/Education:

  • Preferred BS/MS and 6-12 years of experience in ASIC design and STA
  • Previous experience in at least 3-4 product developments
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