Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix's history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.
|Position Profile Name:||Software Engineer, Machine Learning Software Stack|
|Type of Position:||Regular, Exempt|
|Reports to:||Sr. Director, Software Engineering|
|Location:||Santa Clara, California|
At Achronix Semiconductor we develop FPGA-based hardware, software, and systems solutions to accelerate critical applications in areas such at 5G wireless infrastructure, network switching, and datacenter services. We work in small highly motivated teams of domain experts across the full product range, from high-level systems software to digital and analog circuit design, to create innovative products that are first-to-market and solve critical business needs.
You will drive the effort to develop a complete software stack for an FPGA-based machine learning inference accelerator card reference platform. You will adapt existing open-source and university software when possible, and develop new software from scratch as needed, to assemble a complete full-stack, end-to-end software solution. You will work closely with sales, marketing, systems engineering, EDA tool developers, and FPGA architects to support diverse use models from FPGA micro-architecture exploration, memory subsystem design optimization, place-and-route software verification, system prototyping, pre-sales demonstration development, and customer deployment and scaling.
Prior experience is required working with a machine learning accelerator micro-architecture and ISA, as well as current knowledge of state-of-the-art research. You must have a background in open-source compiler hacking. Experience desired with compiler intermediate representations (IRs) and back-ends, JIT compilers, as well as kernel-mode and user-mode runtime environments and device drivers. Familiarity is desired with industry-standard machine learning frameworks, acceleration libraries, domain-specific languages, and with common DNN models.
- Two years of work or educational experience in machine leaning accelerator micro-architectures and compilers
- Skilled practitioner in C++ or Java.
- Experience in Python, Verilog, and System-C.
- Experience required in one of more of the following:
- Machine learning accelerators such as OpenTPU, NVDLA, VTA, EIC
- Compilers such as Glow, TVM, CLANG, LLVM, or GCC
- Machine learning frameworks such as TensorFlow, PyTorch, Caffe2, and Keras
- Acceleration libraries such as MXNet
- Domain-specific languages such as Halide and Spatial
- Common DNN models such as AlexNet, ResNet50, Inception, YOLO, RNN, and LSTM
- Embedded system runtime environments and device drivers
MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, Applied Math, or Physics.Apply Now