Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix's history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

Title: Senior Staff Engineer
Requisition No.: 6400-1023
Type of Position: Regular, Exempt
Reports to: Manager, Hardware Engineering
Location: Bangalore, India
Contact: hr@achronix.com

Job Description/Responsibilities

Primary Responsibilities:

The employee is responsible for the complete physical design of multiple large and complex ASIC and FPGA blocks, and will also contribute to full chip design and integration for Achronix’s FPGA products. The employee is expected to take independent ownership of complex design challenges, which may include:

  • Floorplanning, place and route, and CTS using physical design tools
  • Physical verification
  • Physical integration
  • Physical design methodology
  • STA
  • Bump planning, full chip-level routing and tapeout-ready database creation

The employee is expected to participate in methodology development activities as well as meetings across teams spanning Core technology, System engineering, and Software engineering.

Skills:

  • Expertise in physical design activities: floorplanning, CTS, P&R
  • Expertise in physical verification
  • Expertise with physical design and verification tools
  • A strong understanding of layout DRC rules and concepts, and device identification concepts
  • Strong programming knowledge in Perl, Tcl, and/or Shell scripting
  • Prior experience with bump planning and routing
  • Strong communication skills
  • Ability to work in a dynamic and fast-paced environment with a proactive mindset
  • Experience in 16nm and smaller process nodes is a big plus
  • Experience in custom layout is a plus
  • Working knowledge of ICC2 and ICV is a plus

Experience/Education:

  • Preferred BS/MS and 9+ years of experience in physical design
  • Previous experience in 3-4 VLSI projects in deep submicron technologies
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