Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix's history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

Title: Senior Staff Engineer
Requisition No.: 6400-1013
Type of Position: Regular, Exempt
Reports to: Sr. Manager, Hardware Engineering
Location: Bangalore, India
Contact: hr@achronix.com

Job Description/Responsibilities

Primary Responsibilities:

The employee will be responsible for block-level IP RTL design as well as full chip-level integration RTL design for Achronix’s FPGA products. The employee is expected to take independent ownership of complex design challenges, which may include:

  • Micro-architecture development
  • RTL code development
  • Timing constraints development with STA team
  • Performance modeling
  • Post-Si bring-up
  • Third-party IP analysis and integration
  • System-level reference design creation
  • Automation development for FPGA specific IP generation

The employee is also expected to participate regularly in interactions with global teams spanning System Engineering, Software, and Product Engineering.

Skills:

  • Expertise in micro-architecture development and RTL coding
  • Hands-on experience at the implementation of DDR PHY/Controller with a strong understanding of the die-level and board-level protocol as well as design requirements is a must. Should be able to validate third-party IP for performance/area and SoC integration
  • Automation and scripting experience
  • Excellent verbal and written communication skills
  • Ability to work in a dynamic and fast-paced environment with a proactive mindset
  • Strong knowledge of Network protocols (PCIE or Ethernet) is a big plus
  • Hands-on experience in integrating/Validating System interconnect (AXI interconnect) is a plus
  • Experience with system level performance modeling is a plus
  • Experience with post-Si bring-up and debug is a plus
  • Experience with synthesis and STA is a plus

Experience/Education:

  • Preferred BS/MS and 9+ years of experience in RTL design and verification
  • Previous experience in at least 3-4 product developments, including post-Si bring-up
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