Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix's history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

Title: Senior Design Engineer
Requisition No.: 6400-1022
Type of Position: Regular, Exempt
Reports to: Sr. Manager, Hardware Engineering
Location: Bangalore, India
Contact: hr@achronix.com

Job Description/Responsibilities

Primary Responsibilities:

The employee will be responsible for module-level RTL verification and for Achronix’s Speedster and Speedcore FPGA products. The employee is expected to take independent ownership of complex design challenges, which may include one or more of the following:

  • Methodology development
  • Functional verification at module-level and full chip-level
  • Testbench design
  • ATE functional vector generation
  • Module Post-Si support

The employee is also expected to participate regularly in interactions with global teams spanning Systems, Software, and Product Engineering

Skills:

  • Expertise in verification methodologies, especially OVM/UVM
  • Very strong automation and scripting experience, especially in Python and/or Perl
  • Strong verbal and written communication skills
  • Experience with post-Si bring-up and debug is a plus
  • Ability to work in a dynamic and fast-paced environment with a proactive mindset
  • Strong knowledge of DDR/GPIO PHYs and memory controllers or high-speed serial link protocols (such as PCIe, Ethernet, SATA, XAUI etc.) is a plus
  • Experience with formal verification tools is a plus

Experience/Education:

  • Preferred BS/MS and 3-8 years of experience in RTL design and verification
  • Previous experience in at least 2 product developments
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