Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix's history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

Title: Senior Design Engineer
Requisition No.: 6400-1027
Type of Position: Regular, Exempt
Reports to: Manager, Hardware Engineering
Location: Bangalore, India

Job Description/Responsibilities

Primary Responsibilities:

The employee is responsible for complete physical design of large and complex ASIC and FPGA blocks. The employee is expected to take independent ownership of reasonably complex design challenges, which may include:

  • Floorplanning, place and route, and CTS using physical design tools
  • Physical verification
  • Physical integration
  • Physical design methodology
  • STA

The employee may also be expected to contribute to methodology development activities.


  • Expertise in physical design activities: floorplanning, CTS, P&R, STA, physical verification
  • Expertise with physical design tools
  • A good understanding of layout DRC rules and concepts, and device identification concepts
  • Strong programming knowledge in Perl, Tcl, and/or Shell scripting
  • Good communication skills
  • Ability to work in a dynamic and fast-paced environment with a proactive mindset
  • Experience in 16nm and smaller process nodes is a plus
  • Experience in custom layout is a plus
  • Working knowledge of ICC2 and ICV is a plus


  • Preferred BS/MS and 3-8 years of experience in physical design
  • Previous experience in a 2-3 VLSI project in deep submicron technologies
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