Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix's history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

Position Profile Name:    Hardware Engineer – Physical Design, Core Technology
Requisition No.: #6200-1010
Type of Position: Regular, Exempt
Reports to: Sr. Hardware Engineering Manager, Core Technology
Location: Santa Clara, California
Contact: hr@achronix.com

Job Description/Responsibilities

The Core Technology team at Achronix owns the reconfigurable fabric (look-up tables, routing, configuration memory, carry chains, register files, multipliers, etc.) for our company’s FPGAs.  Members of our team participate in all phases of the FPGA product-development cycle, from architecture conception to circuit design and implementation to high-volume manufacturing. New employees will have the opportunity to contribute to all of these phases and work with the world’s most advanced process technology.

The employee will work on the design, implementation, and characterization of full-custom, high-performance digital logic in 14nm/16nm and below. The employee will share responsibilities across design and verification. His or her responsibilities will include the following:

Primary Job Responsibilities

  • CMOS circuit design of different macros in the FPGA fabric (full-custom portion of the FPGA), including clock distribution in the fabric.
  • Track planning over the fabric, evaluating performance of various metals in the interconnect stack.
  • Timing, EM, and IR flows and methodologies for the fabric.
  • Library characterization of custom standard-cell library cells.
  • Assist in the physical design of fabric IP using industry-standard place-and-route tools (RTL to GDS).
  • Collaborate with other members of the team to optimize our physical design and verification methodologies.
  • Estimate power, performance, and area of RTL blocks both before and after physical implementation.
  • Develop design methodologies and guidelines for each process node.
  • Work closely with foundry employees on process development, customer support, EDA, reliability, test, and product qualification.
  • Develop automated processes for block-level and system-level verification.

Required Skills

  • Experience with digital VLSI CMOS circuit design and physical design in advanced FinFet technology nodes.
  • Experience with schematic entry, netlist generation, and SPICE simulation.
  • Understanding of layout, layout-dependent effects, and parasitic effects.
  • Comfortable with physical design, verification, and analysis tools from vendors such as Synopsys and Ansys.
  • Comfortable designing flows and methodologies from scratch and maintaining them.
  • Excellent debugging skills.
  • Experience with digital VLSI design.
  • Experience reading and writing RTL (e.g., Verilog).
  • Experience with commercial ASIC CAD tools (e.g. DC, ICC, PrimeTime, Totem).
  • Experience with commercial CAD flows (LVS, DRC, simulation, etc.).
  • Familiarity with object-oriented programming concepts is a plus.
  • Familiarity with revision-control systems (e.g., perforce, git) is a plus.
  • Familiarity with using and/or designing FPGAs is a plus.
  • Familiarity with hardware protocols such as Ethernet, PCIe, and DDR3/4 is a plus.
  • Well organized, punctual, and excellent communication skills.

Education and Experience

  • MS in electrical engineering or computer science +2-10 years experience
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