FPGAs are increasingly being used as processing elements in applications that, until recently, were reserved for traditional CPUs. A common configuration is a dual-processing system with the FPGA acting as an accelerating co-processor offloading and enhancing the performance of the CPU. Achronix’s Speedster22i devices are an ideal platform for such acceleration and offload.

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Support for QPI enables the FPGA and CPU to work efficiently as a tightly-coupled unit, sharing memory-space and seamlessly exchanging information, with each device doing what it does best. Also each device maintains its own local memory with quick, low-latency access to the memory-space of its companion device(s).

Speedster22i devices provide hardened IP blocks implementing:

  • 10/40/100 gigabit Ethernet
  • DDR3 memory controllers

These interfaces are fully embedded in the devices, allowing the FPGA to perform more tasks, potentially absorbing the functions of other devices, thereby, lowering device count and complexity.

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Requirements

  • Substantial data path bandwidth for high traffic volume
  • Substantial external memory capacity for traffic buffering
  • Substantial external memory bandwidth
  • Substantial login capacity to implement complex queuing algorithms
  • Substantial internal memory for queuing pointers, policy tables and scratchpad RAM

Provided by Speedster22i FPGAs:

  • Up to 200 Gigabit Ethernet and 200 Gigabit Interlaken
  • Up to six independent DDR3 ×72 interfaces at 1600 Mbps
  • Up to 691 Gbps of raw memory bandwidth
  • Up to 1 million effective LUTs
  • Up to 86 Mb of internal SRAM

Speedster22i devices contain hard IP blocks for the interfaces described above. These fully-hardened IP blocks provide the following benefits:

  • Consume no programmable resources (LUTs, memory and routing)
  • Require no timing-closure (timing guaranteed by design)
  • Consume less power
  • Contribute less latency
  • Require no license fees
  • Fully bypassable, so that I/O and SerDes lanes can be freely used for other purposes

The hardened nature of these protocol blocks leaves more programmable logic resource capacity, which can be used for additional functions, including:

  • Pattern-matching
  • Protocol translation, such as financial orders
  • Table updates (policy, valuation, pricing or subscriber profiles)
  • Statistics gathering for billing or network management
  • Other functions such as (de)compression, (de)encryption and error detection/correction

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