FPGAs have historically enabled Defense applications to build tailored solutions and because they are not affected by the cyclical nature of the industry itself. Electronic system deployments for government and infrastructure applications have decades-long lifespans. FPGA-based designs can be customized at development time and upgraded post deployment for many purposes. This is particularly important because security measures degrade over long periods of time when they are susceptible to outside threats. Reprogrammability of FPGAs allow a design to be adapted to changing threat profiles and to new attack methods by adding or modifying an IP block specifically designed against those vulnerabilities. FPGAs allows for secured development cycle required in these industries. Critical IP blocks can be added very late in the implementation meaning that large sections of the manufacturing and supply chain will never come into contact with these critical IP blocks, even in their encrypted form.

Speedster7t Solution

Achronix is the only company that offers high-performance, standalone FPGAs, eFPGA IP and FPGA-based chiplets. These different form factors based on the same base FPGA technology enables Military and Government companies to create the optimal solutions for their unique requirements. Additionally, the different form factors can be used a different stages of use. For example, the prototype process can be implemented in Speedster7t standalone FPGAs and then the design can be optimized by incorporating Speedcore embedded FPGA (eFPGA) IP with the same architecture as Speedster7t FPGAs into their core ASIC. The Speedster7t devices have the most advanced encryption and authentication security features to ensure trusted FPGA designs, which allows security engineers to adapt their system designs to changing security landscapes. Achronix’s FPGA technologies permit the design of systems that can be adapted and updated to deal with situations that were not possible to be foreseen beforehand.

 

Application Requirement Speedster7t Value
Need for substantial external connectivity via PCIe and Ethernet
  • Multiple ports of 400G Ethernet and PCIe Gen5
  • Highest performance SerDes – 112 Gbps
  • XSR SerDes for extremely low interface power connection for die-to-die connectivity
Highest memory bandwidth for buffering >1 Tbps Memory hierarchy

  • Up to 16 independent GDDR6 channels at 16 Gbps
  • Up to 4 Tbps of total bandwidth
Wide data-path and high performance FPGA fabric optimized for high throughput data transfer and acceleration

  • Up to 20 Tbps of NoC bandwidth for high-speed, wide-data transfers
  • Traditional bit-wise routing plus new optimized 8-bit bus routing
  • Support for arbitrary number formats, routing structures and memory hierarchy
Substantial logic capacity to implement complex, custom algorithms Scalable family of devices up to 2.6M 6LUTs of logic
Higher precision data formats for edge training efficiency
  • FP16, FP24
  • bfloat16
  • Only FPGA to support Block float 16
 FPGA fabric for high performance compute
  • Highly flexible compute for advanced applications such as beamforming
  • High data bandwidth architecture to support massive compute
  • Parallel packet processing engines to support compute intensive functions such as DPI
  • Optimized AI cores for quick deployments
Substantial internal memory for queuing pointers, internal cache and scratchpad RAM Up to 300 Mbits of internal SRAM