The networking/telecommunication world is continuing its decades-long evolution toward higher data rates, higher traffic volume, a more diverse mix of traffic types, and packet-based protocols, with an overlay of connection-based mechanisms.

High-end networking/telecommunication systems tend to be chassis-based, with multiple line cards connecting external traffic in a multitude of diverse communication formats to the shared switch fabric. The demands on line cards, both raw throughput and intelligent functionality, continue to increase steadily.




Edge networking products, like core networking products, use standard interfaces and benefit from the hard IP blocks (10/40/100 gigabit Ethernet, Interlaken, PCI Express, DDR3 controllers) provided by the Speedster22i family. Bandwidth — memory and data path — is a critical requirement for FPGAs in these applications. For example, the Speedster22i HD1000 provides:

  • 64 bidirectional 10.375 Gpbs SerDes lanes
  • 936 user I/O operating up to 1600 Mbps

These applications again require sophisticated traffic management (queuing and scheduling). In addition, more extensive packet inspection and classification is required. This is because packets tend to be entering the network for the first time, and need to be classified and tagged, according to traffic type, flow identity, and so forth — simplifying the tasks of downstream routing and switching elements.







  • Substantial data path bandwidth for high traffic volume
  • Substantial external memory capacity for traffic buffering
  • Substantial external memory bandwidth
  • Substantial login capacity to implement complex queuing algorithms
  • Substantial internal memory for queuing pointers, policy tables and scratchpad RAM

Provided by Speedster22i FPGAs:

  • Up to 200 Gigabit Ethernet and 200 Gigabit Interlaken
  • Up to six independent DDR3 ×72 interfaces at 1600 Mbps
  • Up to 691 Gbps of raw memory bandwidth
  • Up to 1 million effective LUTs
  • Up to 86 Mb of internal SRAM

Speedster22i devices contain hard IP blocks for the interfaces described above. These fully-hardened IP blocks provide the following benefits:

  • Consume no programmable resources (LUTs, memory and routing)
  • Require no timing-closure (timing guaranteed by design)
  • Consume less power
  • Contribute less latency
  • Require no license fees
  • Fully bypassable, so that I/O and SerDes lanes can be freely used for other purposes

The hard-wired nature of the embedded hard IP protocol blocks leaves more programmable logic capacity, which can be used for additional functions, including;

  • Packet forwarding/classification into distinct flows for QoS guarantees
  • Tables updates (routing QoS policy)
  • Oversubscription management statistics gathering
  • Traffic management (policing, queuing, scheduling and shaping)
  • Other functions like compression/decompression, encryption/decryption and error detection/correction

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