Speedster22i Clock and Reset Networks User Guide (UG027)

Speedster22iHD FPGAs have two hierarchical clock networks: a core clock network and a boundary clock network. The core clock network is the hierarchical network that feeds resources in the FPGA fabric. There are two types of core clock networks: a global and a direct. Both of them have common input sources: Clock input pins and PLL outputs which make up the Clock Generator (CG) and recovered SerDes input clocks. These input sources get channeled in from both the north and south sides of the device, and are then fed into the FPGA core through a central trunk. The boundary clock network is a fully programmable clock network in the IO ring, unique to Speedster22iHD FPGAs, that provides for significant advantages when clocking IO ring resources at high frequencies. The boundary clock network is comprised of a low skew global boundary clock network and a lower jitter local boundary clock network. The inputs to the boundary clock network are CGs. Reset signals generated internally or coming from GPIOs are funneled through the Reset Input Blocks in the device corners into the FPGA core and the IO ring. The IO ring contains a dedicated reset network but for distribution to core logic, the clock network resources described above are used.

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