Release date: September 16, 2019

This guide describes a collection of reference designs that demonstrate some of the advanced features of the Speedster7t FPGA family. They are primarily focused on the machine learning processor (MLP) block which is tightly coupled with a block memory (BRAM). These designs are provided "as-is", with no warranty with regard to fitness of purpose, or direct applicability to a users solution.
ACHRONIX ANNOUNCEMENTS

Achronix Introduces Ground-Breaking FPGA Family, Delivering New Levels of Performance

ACHRONIX ANNOUNCEMENTS

Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDes