Release date: September 19, 2019

The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps, supporting a multitude of interface protocols. This guide provides the user with an architectural overview the this network on chip (NoC) plus usage details.
ACHRONIX ANNOUNCEMENTS

Achronix Introduces Ground-Breaking FPGA Family, Delivering New Levels of Performance

ACHRONIX ANNOUNCEMENTS

Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDes