Release date: October 11, 2019

The Speedster7t FPGA device family provides multiple GDDR6 subsystems that enables the user to fully utilize the high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems. This guide provides the user with technical and architectural details of these subsystems, as well as details on how to configure and instantiate these subsystems in a design.
ACHRONIX ANNOUNCEMENTS

Achronix Introduces Ground-Breaking FPGA Family, Delivering New Levels of Performance

ACHRONIX ANNOUNCEMENTS

Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDes