Release date: April 05, 2019

The Achronix Speedster16t macro cell library provides the user with building blocks that may be instantiated into the user’s design. In this guide, each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.
ACHRONIX ANNOUNCEMENTS

Achronix Introduces Ground-Breaking FPGA Family, Delivering New Levels of Performance

ACHRONIX ANNOUNCEMENTS

Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDes