Release date: November 15, 2017

The Achronix Speedster16t macro cell library provides the user with building blocks that may be instantiated into the user’s design. In this guide, each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.
ACHRONIX ANNOUNCEMENTS

Speedcore eFPGA Technology for SoC Acceleration.

ACHRONIX ANNOUNCEMENTS

Achronix Revenues to Grow 700% Year over Year