Release date: January 11, 2018

During normal SoC operation, the Speedcore eFPGA core requires configuration by the end user. This guide covers the details of how to configure a Speedcore instance via JTAG, CPU, or serial flash interface. Also included are details on the Achronix Configuration Bus (ACB) interface that can be used to program configuration bits for ASIC IP surrounding the Speedcore eFPGA.
ACHRONIX ANNOUNCEMENTS

Speedcore eFPGA Technology for SoC Acceleration.

ACHRONIX ANNOUNCEMENTS

Achronix Revenues to Grow 700% Year over Year