Release date: November 21, 2017

This guide details the design flow for integrating a Speedcore eFPGA into an ASIC, including closing timing across the boundary between the Speedcore instance and the surrounding host ASIC, along with how to perform full-chip simulation.
ACHRONIX ANNOUNCEMENTS

Speedcore eFPGA Technology for SoC Acceleration.

ACHRONIX ANNOUNCEMENTS

Achronix Revenues to Grow 700% Year over Year