Release date: October 23, 2018

This guide details the design flow for integrating a Speedcore eFPGA into an ASIC, including closing timing across the boundary between the Speedcore instance and the surrounding host ASIC, along with how to perform full-chip simulation.
ACHRONIX ANNOUNCEMENTS

Achronix Introduces Ground-Breaking FPGA Family, Delivering New Levels of Performance

ACHRONIX ANNOUNCEMENTS

Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDes