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CAST Compression IP Integrated with Achronix eFPGA Technology for High-Performance, Low-Power Solution to Move and Store Big Data

• Will showcase its technology for 5G wireless, HPC, ADAS and autonomous vehicles, machine learning and computer vision applications
• Speedcore eFPGA validation chip built on TSMC 16nm FinFET+ process technology to be displayed

Santa Clara, Calif., April 26, 2018 –– Achronix Semiconductor Corporation, a leader in field programmable gate array (FPGA)-based hardware accelerator devices and embedded FPGA (eFPGA) intellectual property (IP), will showcase the versatility of its Speedc

• Achronix’s Increased Revenue, Expanding Workforce Drives Move to Larger Corporate Headquarters
• Move Designed to Accommodate 2018 Outlook, Growing Number of Employees to Support Technology Portfolio

Santa Clara, Calif., April 25, 2018 –– Achronix Semiconductor Corporation today capped a year-long string of successes, including 700% year-over-year revenue growth and an expanding workforce, by opening its new corporate headquarters with a Ribbon-Cutting Ceremony presided ove

• Steve Mensor to present “Embedded FPGA (eFPGA) for Processor and Algorithm Acceleration” at SEE/MAPLD
• Will highlight technology’s application for 5G wireless, HPC, ADAS and autonomous vehicles, machine learning and computer vision

Santa Clara, Calif., May 15, 2018 –– Achronix Semiconductor Corporation, a leader in field programmable gate array (FPGA)-based hardware accelerator devices and embedded FPGA (eFPGA) intellectual property (IP), will demonstrate the versatility of its

• Will profile Speedcore eFPGA IP’s ability to add a programmable fabric to ASIC or SoC designs
• Two IP Track Talks will feature presentations from Achronix’s Steve Mensor, Kent Orthner

Santa Clara, Calif., June 19, 2018 –– Achronix  will demonstrate Speedcore eFPGA solutions at the 2018 Design Automation Conference.