The Achronix Blog

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Speedcore Instance

How Big Should your eFPGA be? Here are Some Hints.

Volkan Oktem,Sr. Director of Application

Once you’ve made the correct decision to add Speedcore eFPGA IP to your ASIC or SoC design, the next question you’ll need to answer is how large to make the eFPGA. That’s a multi-dimensional question because Speedcore eFPGAs contain many types of blocks including:

Automotive AI

How to Meet Self-Driving Automotive Design Goals Part 1

Manoj Roge,Vice President and Chief Technologist

Achronix anticipates that the favored self-driving architecture of the future will be increasingly decentralized. However, both the centralized and decentralized architectural design approaches will require hardware acceleration in the form of far more lookaside coprocessing than is currently realized.

ADAS SoC

How to Meet Self-Driving Automotive Design Goals Part 2

Manoj Roge,VP of Strategic Planning & Business Development

Today, the advanced driver-assistance systems (ADAS) processor market is growing by more than 25% per year. This growth is driven by the migration of ADAS features – including automatic emergency braking, lane-changing assist, and adaptive cruise-control functions – from luxury vehicles to midrange and even entry-level vehicles. ADAS features will be almost universal by the middle of the next decade.

eFPGA IP

How to Select the Right eFPGA IP Technology Partner

Bob Siller,Director, Product Marketing

An eFPGA is a licensable FPGA IP core that can be embedded into a custom ASIC or SoC just like any other licensable silicon IP core. In evaluating eFPGA IP technology providers, it is important to look at critical factors to help determine if the solution is best for your application.

Speedstet7t NoC Improves Performance

Increase Performance Using an FPGA with 2D NoC

Huang Lun,Sr. Field Applications Engineer

Achronix Speedster7t FPGAs feature a revolutionary new two-dimensional network on chip (NoC), which provides >20 Tbps ultra-high bandwidth connectivity to external high-speed interfaces and for routing data within the programmable logic fabric. The NoC is structured as a series of rows and columns spread across the Speedster7t FPGA fabric. Each row or column has two 256-bit data paths using industry standard AXI data format, which support 512 Gbps data rates.

Next FPGA

Insights from the Next FPGA Platform Event

Manoj Roge,VP of Strategic Planning & Business Development

It was exciting to participate in the Next FPGA Platform on January 22nd at the Glasshouse in San Jose. I found it was particularly exciting to have Achronix share in a panel discussion with Xilinx and Intel. The Next Platform co-editors Nicole Hemsoth and Timothy Prickett Morgan did a great job in interviewing experts from FPGA ecosystem with insightful questions. The best part of Next Platform events is their format, where they keep marketing pitches to minimum with no presentations, just discussions. I will summarize a few insights and observations from the event.

Speedcore Timing

Learning to Share - Embedded FPGA Timing Closure

Alok Sanghavi,Sr. Marketing Manager

When we start school as young children, one of the first lessons we learn is how to share (followed quickly by not running with scissors). As our Sr. Director of Systems Engineering, Kent Orthner, discussed at DAC this past June, sharing is also key when it comes to closing timing with embedded FPGAs (eFPGAs). With an eFPGA such as Speedcore IP, the task of closing timing is owned by two people: the ASIC designer, responsible for the design in the host ASIC, and the FPGA designer, responsible for the design targeting the FPGA.

Achronix Blog

Maximizing Data Conversion Efficiency: A Deep Dive Into the Achronix JESD204C Solution

Scott Schweitzer, Director of SmartNIC Product Planning

Discover Achronix's cutting-edge JESD204C solutions on Speedster7t FPGAs, offering high-speed data converter interfaces for your custom ADC/DAC designs. Learn about increased lane rates, robust links, and more. Request a free demo now!

Cryptocurrency Mining

Mine Cryptocurrencies Sooner Part 1

Raymond Nijssen,Vice President, Marketing

Cryptocurrency mining is the process of computing a new cryptocurrency unit based on all the previously found ones. The concept of cryptocurrency is nearly universally recognized by the publicity of the original cryptocurrency, Bitcoin. Cryptocurrencies were supposed to be a broadly democratic currency vehicle not controlled by any one entity, such as banks, governments, or small groups of companies. Much of a cryptocurrency’s acceptance and trustworthiness is based on that proposition. However, with Bitcoin, that is not how it unfolded.

Bitcoin

Mine Cryptocurrencies Sooner Part 2

Raymond Nijssen,Vice President and Chief Technologist

Bitcoin has lost much of its allure due to the concentration of control of the world’s Bitcoin mining resources by a few players in a few locations, as discussed in Part 1 of this blog. In response, the larger, global cryptocurrency community has started to develop alternative cryptocurrencies based on lessons learned from the Bitcoin experience.