Volkan Oktem, Sr. Director of Applications

July 30, 2018

As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to program a bitstream into a Speedcore eFPGA depends on the configuration mode being used, the data width, clock frequency, and of course, the size of the configuration bitstream.

Configuration of the Speedcore eFPGA consists of the following steps:

  • Clearing the Speedcore eFPGA’s configuration memory
  • Configuration bitstream programming
  • Additional control state transitions to sequence resets and to switch the eFPGA from configuration mode to user mode

As discussed in part 1 of this blog, the Speedcore eFPGA’s FPGA control unit (FCU) handles all three of these tasks. The time required to execute these tasks depends on many factors but especially on the configuration mode. As a reminder from part 1 of this blog post, the Speedcore eFPGA has three configuration modes: Serial Flash (SPI), CPU, and JTAG. The FCU’s configuration-mode pins along with a register-based setting in the Speedcore eFPGA’s JTAG controller select the configuration mode.

In the CPU and JTAG configuration modes, the Speedcore eFPGA acts as a slave and accepts a programming clock in addition to commands and configuration data from the CPU or the JTAG master. In Serial Flash configuration mode, the Speedcore eFPGA acts as a master and supplies a clock to the attached  to a single SPI serial NOR flash memory (for the x1 flash configuration) or to four flash memory ICs (for the x4 flash configuration).

Calculating the Configuration Programming Time

Bitstream programming time dominates the other task-execution times for the CPU and Serial Flash configuration modes. This fact makes estimating the configuration time for these modes straightforward. The configuration programming time for these two configuration modes is calculated simply using the equation:

(The number of bits being programmed / data width) × clock period

This equation produces a configuration-time estimate, but the required configuration time in CPU mode may also depend on the software drivers and interface used. Also, note that the JTAG configuration mode incurs additional JTAG protocol overhead, which increases the configuration time.

The data width variable in the above equation varies with the implementation of the Speedcore eFPGA in the ASIC or SoC. For the CPU configuration mode, the bit width can be 1, 8, 16, 32, or 128 bits. For the Flash configuration mode, the bit width can be either 1 or 4 bits wide. The maximum clock rate for both of these configuration modes is 100 MHz, so the minimum clock period is 10 nanoseconds.

The remaining factor needed to complete the above equation is the number of configuration bits to be programmed. A conservative estimate puts the number of configuration bits in a Speedcore eFPGA at 40 million configuration bits for 100K LUTs.

Rolling all of these factors together produces the following table showing estimated, worst-case configuration times.

Table: Estimated Worst-Case Configuration Times for Speedcore eFPGAs (Estimated times are in milliseconds and assume a 100MHz clock)

Programming Mode
CPU ×128 CPU ×32 CPU ×16 CPU ×8 CPU ×1 SPI ×4 SPI ×1 JTAG
50K LUT 1.8 7.0 14 28 224 56 224 300
100K LUT 3.4 12.5 25 50 400 100 400 800
200K LUT 6.4 24.0 48 96 768 192 768 1,500

The table above shows estimated, worst-case times. You can expect typical configuration times to be about 30%-40% lower than the worst-case times listed in the table.

In all but one case for the largest configuration, as shown in Table 1, the Speedcore eFPGA requires less than one second for configuration. The maximum bitstream configuration data rate in the CPU configuration mode with a 128-bit parallel interface running at 100 MHz is a brisk 12.8 Gb/s, which results in configuration times of less than 10 milliseconds. Clearly, you’ll get the fastest configuration time from the CPU configuration mode using a 128-bit parallel interface.

Note: More detailed configuration bitstream sizing equations appear in the Speedcore Configuration User Guide (UG061).


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