Mountain View, California, USA
Synopsys technology is at the heart of innovations that are changing the way we work and play. Autonomous vehicles. Artificial intelligence. The cloud. 5G. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
Powering this new era of digital innovation are advanced silicon chips and exponentially growing amounts of software content―all working together, smartly and securely. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced technologies for chip design, verification, IP integration, and application security testing. We help our customers innovate from silicon to software, so they can deliver Smart, Secure Everything.
Synplify is the industry’s most advanced FPGA design and debug environment. The Synplify synthesis tools provide fast runtime, performance, area optimization for cost and power and broad language support. Synplify includes features that automate the creation of highly reliable designs such as those used in automotive, industrial, and aerospace and defense applications.
Allows designers to instrument designs and set customized sample and triggers for viewing waveforms. Then the FPGA is debugged with the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware in real-time with traceability from FPGA to RTL.
Using many advanced algorithms and analysis techniques, the SpyGlass platform provides designers with insight about their design, early in the process at RTL. It functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.
The VC Formal solution consistently delivers highest performance and capacity, with more design bugs found, more proofs on larger designs and achieves faster coverage closure through the native integration with VCS and Verdi solutions.
Synopsys VCS functional verification solution provides the industry’s highest performance simulation and constraint solver engines. VCS’ simulation engine supports multicore with state-of-the-art Fine-Grained Parallelism (FGP) technology, enabling users to highly accelerate suitable high-activity long-cycle tests.
Verdi enables comprehensive debug for all design and verification flows. It includes powerful technology that helps you comprehend complex and unfamiliar design behavior, automate difficult and tedious debug processes and unify diverse and complicated design environments.
Synopsys VC Verification IP (VIP) provides access to the industry’s latest protocols, interfaces and memories required to verify designs. Deployed across thousands of projects, Synopsys VIP supports Arm AMBA, CCIX, Ethernet, MIPI, PCIe, USB, DRAM and FLASH memory, automotive, display, storage, and other BUS/interface protocols.
FPGA hardware designers face challenges due to the growing size and complexity of FPGA devices and need the right tools and methodology to complete their designs. The Synopsys FPGA Platform is a design, verification and debug solution that provides developers with a methodology to successfully find and fix bugs earlier in the design cycle.
- Verify design with SpyGlass static, VC Formal, VCS simulation, and Verification IP
- Design using Synplify synthesis
- Debug design with Verdi debug and Identify RTL Debugger
The combination of upfront verification planning, static and formal verification, simulation, synthesis and debug helps to successfully shorten time-to-revenue and minimize schedule risks.