Achronix Semiconductor Corporation

A key component of the Speedster^® value proposition is the availability of 10.3 Gbps embedded SerDes that support multiple standards. The Achronix embedded SerDes (up to 40 lanes) enable extremely high throughput while requiring very few pins. For this reason, SerDes functionality forms the basis for the datapath interface standards most commonly used in today’s designs.

Standard high-speed serial interfaces supported by the Speedster family include:

In addition to these standards, the SerDes also supports proprietary (non-standard) interfaces – often used by system architects for “internal” traffic, where standards are less important, since they are hidden from system connections to the external world. Probably the most important proprietary use of SerDes technology is for backplane interconnect. In backplanes, narrow high-speed SerDes interfaces are preferred because they:

• Minimize signal count
• Don’t require de-skewing of a large number of lanes
• Dispense with the need for a separate clock signal
• Include the ability to adapt to the specific intervening channels

The last (adaptability) feature is most critical for high-rate signaling across impaired channels such as backplanes, which inevitably include connectors and vias, as well as dispersive loss. Speedster SerDes provide significant adaptability:

• Transmitter:
  
  • Linear boost and equalization
  • Digital Feed-Forward Equalization (FFE)
    
• Receiver:
  • Linear boost and equalization
  • Digital Decision Feedback Equalization (DFE)