Achronix Semiconductor Corporation

Achronix FPGAs have a conventional high-speed I/O frame surrounding the picoPIPE™ logic fabric.  Each programmable I/O can be configured to conform to a large number of I/O standards, both single ended and differential.  The I/O frame includes configurable I/Os, SerDes , clock buffers, phased lock loops (PLLs), etc. The I/O frame provides off-chip interfaces and forms the boundary between the picoPIPE logic fabric and the following interfaces:

Industry standard datapath interfaces supported:

Industry standard memory interfaces supported:

• DDR3 SDRAM (1066 Mbps)
• RLDRAM II (1066 Mbps)
• DDR2 SDRAM (800 Mbps)
• DDR1 SDRAM (400 Mbps)
• QDRII SRAM (800 Mbps)
• QDR SRAM (400 Mbps)
• SDR SDRAM (200 Mbps)

All data entering and exiting the picoPIPE logic fabric passes through the I/O frame.  A dedicated byte-lane network with required input and output registers supports the implementation of double data rate interfaces.

These byte-lane networks are very useful for source-synchronous interfaces because they seamlessly integrate with the dedicated internal DDR/DDR2/DDR3 controller. The flexible byte-lane network exists independent of the dedicated controller allowing it to be used when implementing QDRII or RLDRAM interfaces.

Achronix programmable I/Os are deployed in banks and all I/Os within a bank share a common supply and voltage reference.  Each bank has an independent compensation controller to provide accurate process, voltage, and temperature (PVT) compensated driver output impedance and on-die termination via external reference resistors.

Achronix programmable I/Os also have configuration options:

• Slew rate control
• Drive strength control
• Schmitt trigger on inputs
• 3-state options for bus hold, pull-up, or pull-down.

Achronix programmable I/Os include full support for IEEE 1149.1 JTAG Boundary Scan I/O test requirements.