Achronix Semiconductor Corporation

In system design using FPGAs, access to external memory is almost always a critical element. Packet networking applications are especially demanding of high-performance memory, with multiple typical uses:

• Packet buffering (parking packets awaiting modification and/or transmission)
• Routing lookups (MAC address for switches, IP for routers, etc.)
• Policy lookups (subscriber info, QoS information for scheduling packet flows, etc.)
• Statistics gathering

Other applications have analogous needs:

• Frame buffering (video, storage, TDM telecom)
• Routing lookups (video or storage networking)
• “Context” lookups (encryption keys, FIR coefficients, correlation waveforms, etc.)
• Statistics gathering (all apps)

Each of these memory applications imposes its own particular requirements on the memory interface. For example, store-and-forward frame buffering demands high throughput. If most traffic is routed through the memories, the memory throughput must match that of the line interface. Memory will typically be accessed in contiguous “chunks”, so that single-access latency is not the top priority, thus DDR2/3 SDRAM is a common choice for such applications. On the other hand, sequences of unrelated, isolated lookups, such as for routing or policy, place a higher demand on single-access latency.

A further consideration is the balance between reads and writes. Depending on this balance, DDR SRAM or QDR SRAM may be the better choice. Of course, cost is always a factor, and RLDRAM may provide a compromise solution. The Speedster^® family uses versatile, high-performance I/Os that are suitable for all the above memory interfaces, with impressive I/O performance:

• DDR3 at 1066 Mbps
• QDRII+ at 800 Mbps
• RLDRAMII at 1066 Mbps

In addition, all Speedster devices contain dedicated PHY logic and dedicated DDR1/DDR2/DDR3 controllers that can seamlessly be used together.  Speedster devices can support:

• Up to 4 independent 72-bit interfaces (SPD60 and above)
• Up to 2 independent 72-bit interfaces (SPD20 and SPD40)

These dedicated controllers permit the efficient use of high-performance DDR, DDR2, and DDR3 SDRAM, without consuming FPGA logic resource and without incurring any IP licensing fee.  If the controllers are not used the PHY logic can still be used with a user logic implementation for the controller.

For these reasons, among others, Speedster FPGAs are the ideal platform for the many applications that depend on high-performance external memory use.