 Several trends have awakened interest in the use of FPGAs as processing platforms – performing functions normally thought of as appropriate for traditional general-purpose processors (which sequentially execute instructions from a stored program). These trends include:
The last of these trends is epitomized by the emergence of the Speedster® family of FPGAs from Achronix, which offers unprecedented 1.5 GHz FPGA performance. This has created an opening for FPGA-based acceleration. FPGAs have an inherent advantage since they can be configured to perform the target function in hardware – without the overhead of support for a broad instruction set, many of whose instructions are probably not used, or of the need to fetch and execute instructions. This same efficiency also conserves power since the fetches and decodes that unnecessarily consume time also unnecessarily consume power. Some example uses of FPGAs in this way are:
In particular, the following fields have pioneered this use of FPGAs:
An interesting, and increasingly common, approach is to start with a reference design for a symmetric multiprocessing system (using a low-latency interconnect bus), and to simply replace one (or more) of the processors with an FPGA (or FPGAs). This is known as the “socket filler” model, and of course requires that the FPGA bus-interface emulate that of a processor, so that there is no functional difference from the bus point of view. Speedster-based acceleration relies not only on its 1.5 GHz logic performance, but also on its impressive memory bandwidth – which is maximized by the availability of embedded RAM blocks. Considered as a whole, these memories present an extremely wide aggregate interface to the FPGA core logic. When, as in the Speedster family, both memory and logic operate at 1.5 GHz, and the embedded memory bandwidth is supplemented by up to 288 bits of DDR3 at 1066 Mbps, the resulting processing performance is truly impressive. In addition to its clear performance advantages, the Speedster family provides support for all the relevant computing interconnects (both “generic, loosely-coupled” and “low-latency, tightly-coupled”):
The Speedster family and its performance advantage are revolutionizing FPGA usage in high-performance computing, as well as in other performance-intensive applications that can benefit from reprogrammability. The advantage is available without requiring the user to adapt in any way, or even to be aware of the fundamental technical advances enabling it. Speedster truly delivers performance without pain! |